Mapping Tree-Shaped Workflows on Memory-Heterogeneous Architectures

Directed acyclic graphs are commonly used to model scientific workflows, by expressing dependencies between tasks, as well the resource requirements of workflow. As a special case, rooted directed trees occur in several applications. Since typical workflows modeled huge trees, it is crucial schedule them efficiently. We investigate partitioning and mapping tree-shaped on target architectures where each processor can have different memory size. Our three-step heuristic adapts extends previous work for homogeneous clusters. In particular, we design novel algorithm assign subtrees processors with sizes, show how select appropriate when splitting or merging subtrees. The experiments demonstrate that exploiting heterogeneity reduces makespan significantly compared state art memories.